The present invention relates to metal/insulator interconnect structures found in Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging, and more particularly to interconnect structures comprising fluorine-containing, low dielectric constant (low-k) dielectrics. Dielectric treatment methods for mitigating reliability problems associated with out-diffusion of fluorine from the low-k dielectric into other parts of such structures are taught.
Device interconnections in Very Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated (ULSI) semiconductor chips are typically effected by multilevel interconnect structures containing patterns of metal wiring layers called traces. Wiring structures within a given trace or level of wiring are separated by an intralevel dielectric, while the individual wiring levels are separated from each other by layers of an interlevel dielectric. conductive vias are formed in the interlevel dielectric to provide interlevel contacts between the wiring traces.
By means of their effects on signal propagation delays, the materials and layout of these interconnect structures can substantially impact chip speed, and thus chip performance. Signal propagation delays are due to RC time constants wherein R is the resistance of the on-chip wiring, and C is the effective capacitance between the signal lines and the surrounding conductors in the multilevel interconnection stack. RC time constants are reduced by lowering the specific resistance of the wiring material, and by using interlevel and intralevel dielectrics (ILDs) with lower dielectric constants.
The low dielectric constants of fluorine-containing dielectrics (FCD) such as fluorinated diamond-like-carbon (FDLC), fluorinated silicon oxide (FSO), and fluorinated silicate glass (FSG), make them potentially useful as ILD materials in high performance VLSI and ULSI chips where interconnect wiring capacitance must be minimized. This use for FDLC is discussed by S. A. Cohen et al. in U.S. Pat. No. 5,559,367 which issued Sep. 24, 1996 entitled xe2x80x9cDiamond-like carbon for use in VLSI and ULSI interconnect systems.xe2x80x9d
FDLC films can be fabricated by a variety of methods including sputtering, ion beam sputtering, and dc or rf plasma assisted chemical vapor deposition with a variety of carbon-bearing source materials, as described for non-fluorinated DLC films by A. Grill and B. S. Meyerson, xe2x80x9cDevelopment and Status of Diamond-like Carbon,xe2x80x9d Chapter 5, in Synthetic Diamond: Emerging CVD Science and Technology, editors K. E. Spear and J. P. Dismukes, John Wiley and Sons, New York 1994, and by F. D. Bailey et al. in U.S. Pat. No. 5,470,661 which issued Nov. 28, 1995. However, fluorine-containing ILDs such as FDLC cannot be integrated into these interconnect structures without suitable capping and/or liner layers to prevent fluorine in these FCD""s from reacting with other materials in the interconnect structure during required processing steps at elevated temperatures above 300 C. While ILDs with reduced fluorine contents would be expected to have smaller amounts of fluorine available to react, lower fluorine-content ILDS typically also have undesirably higher k values.
Capping materials such as the insulators silicon oxide and silicon nitride, and the conductive liner materials such as TiN have previously been described for use with fluorine-free ILDs as (i) diffusion barriers (to prevent atoms of wiring material from diffusing into the ILD, from where they may readily diffuse into active device regions), (ii) etch stop and permanent masking materials, and (iii) adhesion layers.
These prior art utilizations of capping and liner materials are illustrated in FIGS. 1, 2, 3A and 3B. FIG. 1 shows a schematic cross section view of a generic, 2-wiring-level interconnect structure 10. Interconnect structure 10 comprises substrate 20, conductive device contacts 30 in a first dielectric 40, a first and second level of conductive wiring (50, 60), and two layers of conductive vias (70, 80) embedded in layers of a second dielectric 90. Contacts to packaging dies are provided by conductive contact pads 100 in a third dielectric 110 and a capping layer or insulating environmental isolation layer 120. Interconnect structure 10 incorporates three capping materials: a conductive capping or liner material 130 lining the sidewalls and bottom surfaces of the conductive wiring and vias, an insulating capping material layer 140 overlying each wiring level over those areas not contacted by an overlying via, and an optional insulating capping layer 150 over some or all (shown) of each layer of dielectric 90. Conductive liner or capping material 130 acts to provide adhesion and prevent metal diffusion into dielectric 90; its conductivity provides electrical redundancy to conductive wiring 60, and allows it to remain in the contact regions between conductive features in different levels. Insulating capping material 140 primarily serves to prevent metal diffusion into the overlying dielectric layers, but can also prevent other potentially undesirable interactions as well as acting as an etch stop. Insulating capping material 150 is optionally left in the structure after use as an etch mask, etch stop, and/or polish stop during interconnect structure fabrication.
Interconnect structure 10 of FIG. 1 would typically be fabricated by Damascene processing in which layers of dielectric are sequentially deposited, patterned to form cavities corresponding to the pattern of conductive material desired, overfilled with the conductive material, and then planarized to remove conductive material above the dielectric. This process is repeated as necessary for each additional layer.
Interconnect structures may also be fabricated by Dual Damascene processing, in which approximately double thicknesses of second dielectric material 90 are patterned with dual relief cavities corresponding to the pattern of a wiring level and its underlying via level. FIG. 2 shows a schematic cross section view of a prior art 2-wiring-level interconnect structure 160 analogous to interconnect structure 10 in FIG. 1, except that the disposition of the capping materials 130 and 150 reflects the Dual Damascene method of processing. For example, since wiring level 60 and its underlying via level 80 are filled with conductive material in the same deposition step, there is no conductive cap material 130 between 50 and 70, a characteristic distinguishing feature of all Dual Damascene processed interconnect structures.
FIGS. 3A and 3B show two other Dual Damascene processed interconnect structures similar to interconnect structure 160 of FIG. 2, but different in the presence of insulating cap layer 170, used as an etch stop to facilitate the patterning of the dual relief cavities in the double (via plus wiring level) layers of the second dielectric material 90. In interconnect structure 180 in FIG. 3A, exposed regions of etch stop layer 170 are not removed before filling the dual relief cavities with conductive material; in interconnect structure 190 in FIG. 3B, exposed regions of etch stop layer 170 are removed before filling the dual relief cavities with conductive material.
While the interconnect structures 10, 160, 180 and 190 show two wiring levels, the number of wiring levels may be as few as one or as many as ten or more. In FIGS. 2, 3A and 3B like references are used for functions corresponding to the apparatus of an earlier Figure.
In interconnect structures wherein FCD""s are introduced in place of the dielectric layers such as 90 and 110 in FIGS. 1 to 3B, delamination is encountered during the deposition of cap layers such as cap material 120 and 140 and liners such as 130 if elevated temperatures are required during their deposition. Even if the structure survives the deposition step, delamination can also occur during subsequent processing steps that require temperature excursions in excess of 300xc2x0 C. For example, capping material delamination and cracking was observed in cap/FDLC (1000 nm)/Si samples after a 350xc2x0 C./4 hr anneal in He. Delamination and cracking were present even in samples in which the FDLC forming the third dielectric layer 110 had been given a xe2x80x9cstabilizationxe2x80x9d anneal (400xc2x0 C. in He for 4 hours) prior to capping.
It should be noted that the need for permanent capping and liner materials in interconnect wiring structures would be substantially lessened with the use of ILD""s formulated to additionally function as diffusion barriers. However, the delamination problems described above would still be a concern due to the use of these same capping/liner materials as temporary etch stops and/or hard mask materials.
It is thus an object of this invention to provide a high performance interconnect structure comprising one or more layers of uniquely conditioned and stabilized fluorine-containing dielectric insulation and one or more conductive wiring levels electrically connected by conductive vias, the wiring levels and vias optionally isolated from the fluorine-containing dielectric by current state-of-the-art insulating cap materials which may or may not be fluorine-resistant. It should be noted that the term xe2x80x9cfluorine-resistantxe2x80x9d is meant to describe materials that do not readily react with fluorine to form fluorine-containing compounds that interfere with the function or the mechanical integrity of the interconnect structure. One set of such fluorine-resistant materials is Al, Co and Cr which do not form volatile fluorides by reaction with fluorine at temperatures below 400xc2x0 C.
It is yet another object of this invention to provide a high performance interconnect structure comprising one or more layers of uniquely conditioned and stabilized fluorine-containing dielectric insulation and one or more conductive wiring levels electrically connected by conductive vias, the wiring levels and vias completely isolated from the fluorine-containing dielectric by current state-of-the-art insulating cap materials which may or may not be fluorine-resistant.
It is a further object of this invention to provide a high performance interconnect structure comprising one or more layers of uniquely conditioned and stabilized fluorine-containing dielectric insulation and one or more conductive wiring levels electrically connected by conductive vias, the wiring levels and vias being isolated from the fluorine-containing dielectric on a first set of selected surfaces by a state-of-the-art electrically insulating capping material which may or may not be fluorine-resistant, and isolated from the fluorine-containing dielectric on a second set of selected surfaces by a state-of-the-art electrically conductive capping and/or liner material which may or may not be fluorine-resistant.
The present invention relates to metal/insulator interconnect structures found in Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging, and more particularly to interconnect structures comprising fluorine-containing dielectrics (FCD), such as low-k FCD""s with or without state-of-the-art capping and/or liner materials selected primarily to prevent reliability problems associated with delamination of the various interfaces, and the out-diffusion of the conductor metal through the dielectric. Delamination problems between the fluorine-containing dielectric and the current state-of-the-art capping layers or liners are obviated by reducing the concentration of fluorine in the region of the fluorine-containing dielectric (FCD) near the FCD-capping/liner layer interface. This reduction is achieved through a combination of ultraviolet irradiation and thermal annealing of the FCD to remove fluorine from the near-interface region. By virtue of this conditioning and stabilization of the FCD, the selection of the capping layers and liners are not constrained by a need to be fluorine-resistant, thus facilitating a broader choice of materials and processing options.
The invention further provides an interconnect structure comprising one or more layers of conductive wiring patterns electrically connected by conductive vias; one or more layers of fluorine-containing dielectric (FCD) between at least some of the conductive wiring patterns; the FCD modified so that at least some interfaces of the FCD with other materials in the interconnect structure are provided with a near-interface region that extends from the interface into the FCD and has a substantially lower fluorine content. The FCD may be selected from the group consisting of fluorinated diamond like carbon (FDLC); FDLC with additives selected from the group consisting of H, Si, Ge, O, and N; fluorinated silicon oxide (FSO); fluorinated silicate glass (FSG); organo-inorganic dielectrics containing fluorine; and organic dielectrics containing fluorine.
The invention further provides a method to achieve a reduced-fluorine content region in a fluorine containing dielectric layer comprising the steps of exposing the region in the FCD layer to ultraviolet radiation to at least partially disrupt at least some of the bonded fluorine in the region; and annealing the region in the FCD layer at an elevated temperature for a certain duration to liberate at least some of the at least partially disrupted fluorine from the region thereby making the region substantially lower in fluorine concentration. At least some of the step of annealing may occur concurrently with the step of exposing the region in the FCD layer to ultraviolet radiation.